4-3. RECEIVE AUDIO/DATA SIGNAL PATH. Continued
Plain-Text Data. Continued
The data output from the bit sync and digital squelch network is routed through PT/CT switches on the bit sync
module, FSK detector module, and data processor module. The code correlator on the data processor module
checks for presence of the 15-bit (see para 4-2) code word. if no code is detected, the data processor supplies
a control signal (NO CODE DET) which sets VOICE/FSK select to VOICE.
The data signal is exclusive ORd with the same code signal as was used on transmit. This returns the data to its
original format. Majority logic error correction is applied to improve the bit error rate and the data is returned to
its original low-speed rate. An FSK modulator changes the digital data back to FSK. The data is routed through an
AND/OR select with the FSK/alarm generator signal (used for self-test) on the FSK detector module and returned
to the data processor as AD2 RCV/GEN FSK. After low-pass filtering and amplification it is output to the intercom
as RCV AUD on J2-K and J2-L.
Encrypted voice from the rt enters the dra as XMODE RCV at J1b. A PT/CT switch on the bit sync module
routes the signal out to the KY-58 as CT IN on J3-b. The voice is decrypted in the KY-58 and returned to the dra
as RCV AUDIO on J4-K and J4-L. It goes through PT/CT and VOICE/FSK switches on the data processor, is
amplified by a push-pull driver, and is output to the intercom as RCV AUDIO on J2-K and J2L.
Digital data from the rt is applied to the dra at J1-b. A PT/CT switch on the bit sync module routes the data out to
the KY-58 on J3-b as CT IN. The data is decrypted in the KY-58 and returned to the dra as RCV DIG DATA IN on
J4-C. It is level shifted on the data processor and applied to the code correlator. The code correlator checks for
the presence of the 15-bit code word (see para 42). If no code word is detected, the data processor supplies a
control signal (NO CODE DET) which sets VOICE/FSK select to voice. The data is not exclusive ORd with the
code because it was not on transmit. The data goes to the deinterleaver and from there is processed the same
as PT data.
The dra is located away from the operator in the aircraft. For this reason, the self-test is made to operate every
time power is turned on. The self-test actions are as follows:
test data processor circuits,
l test that FSK detector will detect an internally generated FSK signal,
l test that bit sync module will lock onto an internally generated digital signal.
The self-test sequence begins with the start/stop control on the FSK detector module. See figure FO-13. The
start/stop control resets the timer when the 6.75 V dc starts to rise. At 96 msec, the timer sends a pulse back to
the star! /stop control which causes self-test mode to begin. The timer then times the self-test sequence. If any of
the DRA modules fail self-test, the status correlator on the FSK detector module sends fail signal to the FSK/
alarm generator. The FSK/alarm generator then sends a 1200-Hz alarm tone to the intercom.
To test the FSK detector, the FSK alarm generator sends an FSK signal to the data processor on the AD2 RCV/
GEN FSK line. FSK passes through the low-pass filter and hard limiter to the FSK detector. The FSK detector
circuit signals the status correlator if FSK is detected. If FSK is not detected, an alarm is generated.
To test the bit sync module, an 8-kHz digital clock is connected to the bit sync and digital squelch network. If the
bit sync locks onto the digital signal, the digital squelch signals the status correlator by way of a debouncer on the
data processor. If bit sync does not occur, an alarm is generated.